Investigation of CMOS Based Integration Approach Using DAI Technique for Next Generation Wireless Networks

Abstract

This research work investigates a CMOS based low noise amplifier (LNA) using differential active inductor with eight-shaped patch antenna for next generation wireless communication. The proposed work conceded into three different phases. The first phase proposes LNA architecture which includes multistage cascode amplifier with a gate inductor gain peaking technique. The ground approach for this architecture employs active inductor technique that includes two stages of differential amplifier. The proposed novel technique leads to give incremental in inductance by using of common mode feedback resistor and lowers the undesirable parasitic resistance effect. Additionally, this technique offers gain enhanced noise cancellation and achieves a frequency band of around 5.7\xa0GHz. The proposed architecture includes single stage differential AI and enhances the bandwidth up to 6.8\xa0GHz with peak gain of 21\xa0dB at 7.8\xa0GHz. The noise figure and stability factor are achieved which is reasonably good at 1\xa0dB. The proposed architecture is design and optimized on advanced design RF simulator using 0.045\xa0µm CMOS process technology. While in second phase, a narrow band eight-shaped patch antenna is designed which provides operating band range from 5.8 to 6.5\xa0GHz with 6.2\xa0GHz resonating frequency. Highest peak gain of 15\xa0dB and maximum radiation power of 42.5\xa0dBm is succeed by proposed antenna. The final phase provides integration strategy of LNA with antenna and achieves desired gain of nearly 21\xa0dB with minimum NF of 1.2–1.5\xa0dB in the same band.