A Novel Approach to Investigate the Impact of Hetero-High-K Gate Stack on SiGe Junctionless Gate-All-Around (JL-GAA) MOSFET

Abstract

It is a well-known fact that the gate stacking is used to improve the electrostatic behavior of Si0.5Ge0.5 Junctionless Gate-All-Around (JL-GAA) MOSFETs. In gate stacking, the high-k oxide material is stacked with an interfacial silicon dioxide (SiO2) layer. In the recent past, oxide engineering techniques have been investigated as an alternative approach to improve the driving current of JL-GAA MOSFETs. In this paper, oxide engineering has been applied to improve the electrostatic performance of JL-GAA MOSFETs. The comparative study of the three device structures, namely Double Hetero gate oxide (DHGO), Triple Hetero gate oxide (THGO), and Quadruple Hetero gate oxide (QHGO) has been performed for various performance parameters. The objective behind this investigation is to highlight a significant enhancement in the driving current of JL-GAA MOSFETs. The comprehensive analysis shows that the DHGO device offers the highest ON-current, lowest subthreshold swing, and DIBL. Hence, the proposed device will be a perfect match for low power and high-speed communication systems.