Effect of CNTFET Parameters on Novel High Stable and Low Power: 8T CNTFET SRAM Cell

Abstract

In this paper, we have investigated the stability and power consumption of an 8 transistor (8 T) carbon nanotube field-effect transistor (CNTFET) based static random-access memory (SRAM) cell. The power and noise performances of the proposed 8 T CNTFET SRAM cell are observed for write, hold and read operations. The power consumption and noise margin of the proposed 8 T CNTFET SRAM cell are compared with that of conventional 6 T and 8 T CNTFET SRAM cells. From the simulation results, it is noted that during the write, hold, and read operations, the proposed structure consumes less power than the conventional CNTFET SRAM cells. The proposed 8 T CNTFET SRAM cell provides greater write and hold modes stability than conventional CNTFET SRAM cells, which is measured by calculating static noise margin (SNM). The performance of CNTFET depends on several parameters like dielectric constant (Kox), oxide thickness (Hox), supply voltage, pitch value, and temperature. The effect of these parameters on the power and stability of the conventional and proposed CNTFET SRAM cells are observed. It is noted that the proposed 8 T CNTFET SRAM cell provides good stability during PVT variation and consumes less power than conventional 6 T and 8 T CNTFET SRAM cells. The performance metrics of the proposed 8 T CNTFET SRAM are observed for both pre-layout and post-layout simulations. All the simulations are performed using the Stanford University 32 nm CNTFET model with the HSPICE simulation tool.