Strategies for choosing an appropriate numerical method for FPGA-based HIL

Abstract

Abstract Hardware-In-the-Loop (HIL) has become a very popular approach for power electronics testing in recent years due to its safety and low cost. Furthermore, the outcome of HIL techniques has improved with the incorporation of Field-Programmable Gate Arrays (FPGAs), which allow faster and more accurate real-time simulations. The use of FPGAs in HIL implies some challenges, like the choice of a relevant numerical method for the implementation. The task is not trivial, because the numerical method should be executed in real time and it should obtain the best trade-off between accuracy and hardware resources using the smallest possible computation time. The HIL performance of four popular numerical methods is evaluated in this paper: 1 st order Forward Euler, 2 nd order Adams–Bashforth, 2 nd order Runge–Kutta, and 4 th order Runge–Kutta. Their error results with different simulation time steps and 32- and 64-bit resolutions are calculated. The methods are implemented in FPGA for the simulation of a simple power converter independently and as a part of an HIL system which includes a DAC. The hardware synthesis results are obtained along with the minimum execution time for each method. The results show that even though Runge–Kutta methods get the best accuracy outcome, once accuracy limiting factors in real environments are considered, the simplest methods ( 1 st order Forward Euler and 2 nd order Adams–Bashforth) gain the best overall performance considering Cost Performance Indexes.