Temperature analysis of underlap GAA-SNWTs for analog/RF applications

Abstract

Abstract In the present work, a comprehensive study of temperature on gate-all-around silicon nanowire FETs (GAA-SNWTs) with source/drain underlap is performed to investigate the influence of Air as spacer dielectric, on analog/RF behavior of the device. The transconductance gm of the device enhances when the temperature is dropped down to 100\u202fK. Thus, the analog/RF figure-of-merit (FOM) of the device enhances, rendering the device suitable for low temperature, low-power high-frequency operations. For targeting low power applications, FOMs are elicited at 10\u202fμA/μm. It is perceived that the intrinsic gain of the device is marginally altered for distinct spacer dielectric (Si3N4 and air). Frequencies like cut-off frequency (fT) and maximum oscillation frequency (fMAX) of air spacer dielectric based underlap GAA-SNWTs are enhanced by 2.15 times and 1.73 times respectively when the operating temperature is dropped down to 100\u202fK from 400\u202fK. This results in higher percentage improvement in RF-FOM in terms of transconductance frequency product (TFP), gain-frequency product (GFP), and gain transconductance frequency product (GTFP).