Performance evaluation of single-ended disturb-free CNTFET-based multi-Vt SRAM

Abstract

Abstract We propose a single-ended disturb-free carbon nanotube field effect transistor (CNFET) based stable nine transistors (9T) SRAM cell using multi-threshold (multi-Vt) technology. Simulations of the CNFET 9T SRAM cell, using a CNFET HSPICE model, have shown advantages over the conventional Si-CMOS cell in terms of leakage power consumption, dynamic power consumption, stability, and delay. Due to higher carrier mobility and high ION/IOFF ratio makes the CNFET devices suitable for high-speed nanoelectronics applications. The disturb-free architecture and bit interleaving approach provide error-free operations at the low supply voltage. The proposed SRAM cell implementation for low leakage 16\u202fnm CNFET technologies provides the possibility of high integration density which also significantly reduces 3.2\u202f×\u202fpower consumptions as compared to the conventional cell. The multi-threshold technology is capable of improving simultaneously the leakage current and dynamic power consumption. The proposed SRAM architecture is implemented with write-assist, adaptive supply voltage scaling and the impact of geometrical liability.