A 1 GS/s 10bit SAR ADC with background calibration in 28 nm CMOS

Abstract

Abstract This paper presents a two-channel 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) in 28\xa0nm CMOS. Multi-bit/cycle SAR ADC with redundancy is proposed. Novel background calibration for multi-bit/cycle SAR ADC is applied in the prototype ADC monitoring and calibrating the offset between DACs. The ADC achieves both high speed and low power by combining several features, namely digital calibration, redundancy, foreground calibrated dynamic comparator and leakage-immune dynamic logic. According to the simulation, the proposed calibration technique significantly improves linearity exhibiting 77.69\xa0dB SFDR and 60.95\xa0dB SNDR with Nyquist-frequency input at 1\xa0GS/s sampling rate.