Efficient underdetermined speech signal separation using encompassed Hammersley- Clifford algorithm and hardware implementation

Abstract

Abstract Speech Separation is among the propelled advances for a wide range of uses in different sectors, where detachment from the Blind Source Separation Signal is a troublesome task. Blind source separation is a growing digital signal processing industry to separate the precise signal from the recorded dense. Exclusively, among the Blind Source Separation, the Under Determined Blind Source Separation is considered as an Over Determined Blind Source Separation due to its wide range of usage. Nevertheless, it is seen that real implementation is very rarely done in existing researches because the real-time Implementation of UBSS (Underdetermined Blind Source Separation) exists to be a challenging one due to its lacking hardware characteristics of increased latency, reduced speed and consumption of more memory space. Consequently, an increasing need to implement an Underdetermined source signal separation in real-time with improved hardware utility. In this Unswerving framework, a Real-time feasible Source Signal separator formulated in which the source signals decomposed by Boosted Band-Limited VMD (Variational Mode Decomposition) Multicomponent Signal”. The amount of Band-Limited” Intrinsic Mode Function (BLIMF) was subjected to the Encompassed Hammersley–Clifford algorithm for source separation using Expectation-Maximization and Gibbs Sampling, an alternative to deterministic algorithms and to determine the exact estimated parameter from the E-M method. Subsequently, the source separation algorithm infers the best separation of source signals by exact estimation and determination from the decomposed signals. The iterations in E-M estimation reduced by the Gauss-Seidel Method. Thus, our novel source signal separates internally with a signal decomposer and a source separation algorithm with fewer iterations, which reduces memory consumption and yields better hardware realization with reduced latency and increased speed. The proposed implementation is done by utilizing Matlab for initial processing and the hardware analysis performed in Xilinx Platform.