Modeling of interface trap charges induced degradation in underlap DG and GAA MOSFETs

Abstract

Abstract With the shrinking device geometries, the extremely high electric field in the drain-channel region makes nano-devices more susceptible to Hot Carrier induced Degradation (HCD) effects. This paper develops an HCD degradation model of gate underlap Double Gate (DG) and Gate All Around (GAA) MOSFET due to hot carrier induced interface trap charges (ITCs). The parabolic approximation and conformal mapping techniques are used to solve the 2D Poissons equation to obtain the channel potential function of the device. The modeling results show that the ITCs effect becomes more dominant for scaled-down DG and GAA MOSFETs and can be reduced by the underlap design. The proposed model accurately depicts the interface charges induced degradation on surface potential, threshold voltage, and Drain Induced Barrier Lowering (DIBL). The effect of ITCs on the threshold voltage and DIBL with the variation of underlap length, gate length, oxide thickness and damaged region length are investigated and validated by comparing them with their corresponding TCAD simulation data obtained by using the TCAD Sentaurus. From the results, it is observed that the effect of negative ITCs (NITCs) have more dominant effect in comparison to positive ITCs (PITCs), and GAA with underlap are more immune to the ITCs effect in comparison to DG MOSFETs. The proposed model is useful in reducing short channel effects in DG/GAA devices to increase immunity against SCEs and useful in practical devices.