Energy-aware and fault-tolerant custom topology design method for network-on-chips

Abstract

Abstract The rapid reduction in integrated circuit dimensions makes it possible to place more components on a single chip in each generation. While the increase in components requires a better communication mechanism than traditional wiring-based communication methods, new design algorithms are needed to tolerate increasing permanent failures due to shrinking technology dimensions. To solve the former problem, the network-on-chip (NoC) paradigm was developed to keep pace with the communication demands on these very large systems. This article deals with the latter problem. That is, we provide a fault-tolerant topology generation method that can tolerate single permanent link failure on a NoC architecture that is designed for a particular application. Our generated topologies provide fault-tolerance by providing at least two alternative paths between the application’s communicating nodes. Our method is a genetic algorithm based method, which generates an initial population based on ring topology and produces better irregular topologies in terms of energy consumption through genetic operators. The objective function of the proposed method is to minimize the energy consumption resulting from network communication. We tested our method on several multimedia benchmarks and custom generated graphs and compared it with previous algorithms and the ring topology. Our results show that as the number of application nodes increases, our method achieves better results in a shorter time than the previous method.