Improved galvanic porous silicon fabrication using patterned electrodes

Abstract

Abstract On-chip porous silicon can be fabricated in a number of ways, but perhaps the simplest is a galvanic method that requires no external power supply. While this etch process is relatively simple, the etch is highly dependent on the surface area ratio (SAR) of a backside precious metal and frontside silicon surface, which respectively act as the cathode and the anode of an electrochemical cell. The SAR controls the etch current density, and therefore local variations can create high current densities that have detrimental effects on the quality of the final porous silicon film. The present study investigates the use of patterned backside platinum electrodes with the galvanic etch technique. The use of a patterned backside electrode that mimics the silicon pattern on the frontside, provides a more consistent etch current throughout the entire sample, and thus a more uniform porous silicon film. A triangular shape porous silicon film was tested in this work for comparison to a previous study utilizing an unpatterned electrode. With patterned electrodes, an etch depth variation percentage was observed throughout the length of the film of 8%. This is a considerable improvement over a 108% depth variation observed with a similar frontside silicon pattern and an unpatterned backside electrode.