Comparison of memory effect with voltage or current charging pulse bias in MIS structures based on codoped Si-NCs embedded in SiO2 or HfOx

Abstract

Abstract Co-doped Si-NCs have been introduced into MIS structures gate dielectric layers. The fabricated test devices were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Comparison between results for HfOx and SiO2 gate dielectric layers is shown and discussed. Presented findings are promising for possible applications of Si-NCs in memory structures.