Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices

Abstract

Abstract This paper proposes efficient fixed-point and floating-point implementations for radix-10 decimal logarithm on Xilinx FPGA devices. The technique is based on the digit-recurrence method, which supports the three decimal floating-point (DFP) types specified in the IEEE 754–2008 standard. The novelty of this proposal is that it avoids the implementation of redundant carry-save logic by direct selection (i.e. via scaling). The designs involve novel techniques based on efficient use of dedicated resources in the programmable devices. Implementations were made on Xilinx 7-series devices. For fixed-point logarithm, they are capable of operating up to 145\u202fMHz for p\u202f=\u202f7, 124\u202fMHz for p\u202f=\u202f16 and 108\u202fMHz for p\u202f=\u202f34, and for DFP logarithm the operation frequency obtained was 123\u202fMHz for p\u202f=\u202f7, 104\u202fMHz for p\u202f=\u202f16 and 93\u202fMHz for p\u202f=\u202f34. In contrast to other related works, the proposed architecture achieves better computation times and less occupation in area in terms of LUTs.