An efficient non-separable architecture for Haar wavelet transform with lifting structure

Abstract

Abstract In this paper, a memory efficient, fully integer to integer with parallel architecture for 2-D Haar wavelet transform with lifting scheme has been proposed. The main problem in most 2-D wavelet architecture is the intermediate or internal memory (on-chip), which is mostly proportional to the data size, the increase of the internal memory lead to increases of the die area and control complexity. The proposed algorithm is a non-separable Haar wavelet architecture which is derived by rearranging and combining the lifting steps which are carried in both vertical and horizontal directions and performing it in a simple and single step. In addition to the elimination of internal memory, the proposed algorithm is outperforming the existing architecture in term of hardware utilization, latency, number of arithmetic operation, power consumption, and used area. The proposed algorithm, is fully parallel and that make it suitable to be implanted using FPGA devices. Finally, An FPGA Development board with Zynq series “XC7Z020-1CLG484” has been used as the design platform, and all the results and tables are estimated by the Vivado® Design Suite.