Linear and quadratic time frequency transforms on FPGA using folding technique

Abstract

ABSTRACT In this paper time frequency representations (TFRs) are implemented on FPGA. Linear TFRs such as Short Time Fourier Transform (STFT), Continuous Wavelet Transform (CWT), Stockwell Transform (S-Transform) and Quadratic TFRs like Wigner Ville Distribution (WVD), Pseudo Wigner Ville Distribution (PWVD), Choi William Distribution (CWD), and Rihaczek Distribution (RD) are designed in Verilog and performed over FPGA. In most of the FFT architectures many butterfly unit (BU) stages are remains idle during computation since current stage computation depends on previous stage outputs. As a result these idle BU leads to additional register allocation and delay propagation. An optimized VLSI architecture is proposed in this paper for efficient clock utilization to compute FFT in all TFRs. Folding technique is implemented in all TFRs to minimize the register allocation. The design is carried out in Verilog code and CORDIC algorithm is used tocomputecorebutterflystructureofFFTinallTFRs. Chirp signal is taken as input to evaluate real time performances of all TFRs. Real time factors utilized on FPGA hardware like Flip Flops, IOBs, LUTs utilization and power consumption are compared for allTFRs. Further proposed methodology is compared with previous existing methods for better time frequency applications.