About 250/285 GHz push–push oscillator using differential gate equalisation in digital 65-nm CMOS

Abstract

This study presents a push–push oscillator architecture based on differential gate equalisation to enhance the oscillation frequency while providing relatively high output power with ultra-compact layout form factor. The frequency enhancement is derived as a function of the equivalent RLC model of the oscillator s main constituents. The proposed principle is applied to a terahertz oscillator in the 200–300\u2005GHz range to mitigate the excessive substrate and skin effect losses in standard digital 65-nm complementary metal–oxide–semiconductor technology at such high frequencies. The design concept is validated using two single-stage push–push oscillators. The first oscillator shows −8.1\u2005dBm output power at 250\u2005GHz oscillation frequency and −106.8\u2005dBc/Hz phase noise at 10\u2005MHz offset while consuming 76\u2005mW power from 1.5\u2005V DC supply voltage. The chip area is 200\u2009×\u2009250\u2005μm2. The second oscillator provides −14.8\u2005dBm output power at 285\u2005GHz and −106\u2005dBc/Hz phase noise at 10\u2005MHz offset with 80\u2005mW power consumption from 1.5\u2005V DC supply. The chip area is 200\u2009×\u2009200\u2005μm2.