Methods to design ternary gates and adders

Abstract

This chapter contains various designs of ternary logic gates and adders using complementary metal oxide semiconductor transistors (CMOS) and carbon nanotube field effect transistors (CNTFETs). As the time goes by binary logic is getting harder to implement on smaller scale, so ternary logic becomes a better alternative of the same. Ternary logic has the simplicity over binary logic and it is energy efficient also. In today s world when it s a challenge to implement the circuit design on as small level as possible, binary logic is limited due to large number of interconnects and large chip area, which is reduced in ternary logic. In ternary logic, there is a requirement of the multithreshold transistors, which can switch on and switch off on the particular voltage level when the circuit demands, since CNTFET s threshold can be changed by varying their chirality or tube diameter they have become the most suitable devices to implement ternary logic. In this chapter various research works on ternary gates and adders will be discussed and a comparison between them will be made on various performance parameters such as power delay product (PDP), transistor count and time delay. These parameters are evaluated and compared by simulating these circuits.