A Compact Memory Structure based on 2T1R Against Single-Event Upset in RRAM Arrays

Abstract

The single-event upset (SEU) has significant influence on the reliability of 1-transistor-1-RRAM (1T1R) array due to heavy ion strikes. This paper proposes a compact memory structure based on 2-transistor-1-RRAM (2T1R), which exploits the signal space between adjacent cells in the RRAM array structure. Results show that the proposed structure can successfully alleviate the SEU effect in RRAM array - it eliminates the overhead of 1ns delay and 400pJ power consumption of READ operation, as well as 2ns delay of RESET operation, at the cost of only 1.9% area overhead compared to the 1T2R structure.