A 4.6V, 6-bit, 64GS/s Transmitter in 22nm FDSOI CMOS

Abstract

A 6-bit large-swing, digital transmitter was implemented in a production 22nm FDSOI CMOS technology. It features a 35mA/4.8V series-stacked complementary differential DAC output stage with MOSFET gate finger segmentation and which operates in class-D switching mode. The 1.4 pJ/b efficiency output stage has 10 complementary inputs, 7 for the 3 thermometer-coded MSBs, and 3 for the binary-weighted LSBs, which are driven by 0.8V CMOS inverter chains switching at up to 66 Gb/s. Measurements of 4.6Vpp differential PAM-4 eye diagrams at 52 GBaud are reported using the on-chip PRBS7 generator. With external data signals from a 64Gb/s BERT and only 3/4 of the 7 thermometer-coded output-stage MSB sections switching, the transmitter achieves 56GBaud 5-PAM, 60GBaud 4-PAM, 62GBaud 3-PAM, and 66Gb/s NRZ operation. The transmitter consumes 450 mW, which includes the clock amplifier, PRBS7 generator, serializer, ten 66Gb/s input data paths matched to 50 Ω, and the large-swing 6-bit DAC output stage.