An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique

Abstract

The rise of 5th generation (5G) communication, satellite communication and radars has been boosting the demand for millimeter wave (mm-wave) phased array frontends. Bandwidth and chip area are two crucial performance merits of mm-wave phased array frontends. Wide bandwidth is necessary to support high-speed communications at various 5G frequency bands, or improve the range resolution in radar applications. On one hand, the large area consumption increases the chip cost. One the other hand, in a large-scale phased array system, the maximal allowed chip area for each signal channel is set by the antenna element space, which is usually the half wavelength to avoid grating lobes. It would be very difficult to feed each antenna element if the chip area is too large. A sparse antenna array can relieve the channel area restriction at the cost of possible grating lobes or a narrower beam scanning range. Fig. 1 top-left shows the block diagram and layout floorplan of a typical mm-wave phased array frontend. In mm-wave frontends, on-chip transformer-based matching networks are extensively used due to their compact layout, easy DC bias connection and potential to achieve wideband matching. As shown in the Fig. 1 top-left, the chip area of a mm-wave phased array frontend is dominated by transformers. What makes the situation worse is that the area of on-chip transformers doesn’t scale as much as transistors along with the process advancement. Therefore, transformers are increasingly expensive in the advanced process nodes.