2021 IEEE Custom Integrated Circuits Conference (CICC) | 2021

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture

 
 
 
 
 
 
 

Abstract


Thanks to the noise-shaped comparator, Noise-Shaping SAR (NS-SAR) ADCs offer high resolution and simultaneously inherit the outstanding energy-efficiency from the SAR ADC [1] –[5]. The poor NS efficacy however calls for a large OSR/order to compensate [1], making a wide bandwidth (BW) and together with low power become challenge. The high speed NS-SAR in [2] only allows a passive NS configuration where its NS efficacy is degraded by the residue attenuation. To improve the efficacy while preserving low power, the dynamic amplifier (D-amp) is used in [3] and [4] to obtain the negative poles and optimized zeros, respectively. They however suffer from the slow sequential integration procedure, thus limiting the BW < 5MHz. In [5], the D-amp is adopted to enable both pipeline and 1st-order error feedback (EF) NS where it achieves a decent NS efficacy by incorporating the extra feed-forward (FF) path in the 2nd stage. Nevertheless, the NS effect is weaker than the ideal 2nd-order for stability consideration. In this work, the NS efficacy of SAR-assisted NS pipeline architecture is further extended to 2nd order with optimized zeros, utilizing only a single D-amp. It enables an 8.5 dB superior SQNR than [5] with a small OSR of 6.5. The prototype also includes a split-over-time facilitated offset and gain calibration with a convergence enhancement configuration.

Volume None
Pages 1-2
DOI 10.1109/CICC51472.2021.9431444
Language English
Journal 2021 IEEE Custom Integrated Circuits Conference (CICC)

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