A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET

Abstract

This paper presents a 7GS/s 8-bit time-interleaved SAR ADC instance produced from a generator-based design flow in a 16nm CMOS FinFET technology. Design techniques such as cross-coupled routing and clock delay modulation are utilized for compatibility with a FinFET process. The time-interleaved SAR ADC layout is automatically generated by placing templates and wires on a grid to abstract design rules. The generated ADC instance with digital calibration achieves 38.2dB SNDR, 97.2fJ/conv-step Walden Figure-of-Merit (FoMW), and 150.6dB Schreier Figure-of-Merit (FoMS), consuming 45.2mW from a 0.95V analog supply and a 0.72V digital supply, and occupying 0.157mm2.