A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure

Abstract

This paper presents a capacitive-coupled VCO-based sensor readout featuring a hybrid PLL $- \\Delta \\Sigma \\mathrm {M}$ structure. It leverages phase-locking and PFD array to concurrently perform quantization and DEM, much reducing hardware/power compared to existing VCO-based readouts counting scheme. A low-cost in-cell DWA scheme is presented to enable highly linear tri-level DAC. Fabricated in 40nm CMOS, the prototype readout achieves 78dB SNDR in 10kHz BW, consuming $4.5 \\mu \\mathrm {W}$ and 0.025mm2 active area. With 172dB Schreier FoM, its efficiency advances state-of-the-art VCO-based readouts by $50 \\times $.