A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration

Abstract

This paper presents a split time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) with digital background mismatch calibration. Benefitting from the proposed split TI topology, the mismatch calibration convergence speed is fast without any extra analog circuits. A prototype 10-b 1.6-GS/s 7/8-way split TI-SAR ADC in 28-nm CMOS achieves 54.2dB SNDR at Nyquist rate with a 2.5GHz 3-dB bandwidth, while the power consumption is 12.2mW leading to a Walden FOM of 18.2 fJ per conversion step.