A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique

Abstract

This paper presents a 10-bit 120MS/s SAR ADC. A novel reference ripple cancellation technique is proposed to address the reference settling issue during high-speed DAC switching. Instead of consuming power/area to ensure a fast recovery or small ripple, it provides a feed-forward path for the reference ripple and performs cancellation at the comparator input, thus guaranteeing a ripple-free signal. A 5-bit dedicated DAC is configured to emulate the ripple transfer function of the main DAC. A 40nm CMOS prototype achieves a Walden FoM of 15fJ/c-s while requiring only 3pF decoupling capacitor.