A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-Rejection Passive FIR Filter

Abstract

This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36×36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53× 90μm. Both components are not only small in chip area, but also offer competitive power-efficiency