Front-end Stage Design of a Two-stage Grid-tied PV Inverter

Abstract

Two-stage grid-tied PV inverters with a Boost and an H-bridge inverter are widely used. The efficiency improvement and leakage current suppression are the two main challenges for such a two-stage design. This paper presents a design method for the front-end stage. Firstly, the diodes in the Boost are replaced by the SiC MOSFETs to reduce the conduction loss, and the parameters of the Boost are optimized to increase the efficiency. Secondly, the parasitic capacitors of the SiC MOSFETs are considered, so that the CM filter design in the front-end can compromise the leakage current suppression. The effectiveness and validity are verified on a 1kW two-stage inverter.