A dual threshold voltage modified dynamic power cutoff technique to consolidate leakage and speed in a VLSI subsystem

Abstract

Leakage power is considered a major bottleneck in today s VLSI systems, owing to the continuous demand to accommodate more transistors on chip and make it highly functional. Different dynamic power gating cutoff techniques to reduce leakage current during active switching state are proposed in the past, with no substantial attention shown towards the system performance. The paper proposes a novel technique that employs an existing power gating circuit methodology and attempts to address the performance of the circuit by integrating dual Vt transistors in the critical path and in the power gated paths. The proposed technique was implemented on a repeated structured multiplier digital subsystem block designed in a 45 nm technology. The subsystem is optimally partitioned into different timing groups based on the minimal switching window (MSW) of each gate. Further power gated cutoff transistors were designed with high Vt to operate at an optimized timing window within each clock cycle, resulting in 83% increase in leakage power savings. In addition, low Vt cells were designed in the computational block to improve the overall computation speed, and reduce the number of operational windows. The dynamic power gating cutoff technique in addition to Dual Vt cells improves the performance of the circuit when compared to employing only power gated cutoff transistors, while maintaining impressive leakage power savings of 66.66%.