Reduction of Electrical Signal Interference for future IC Integration-An Extensive Review

Abstract

As per Moore s law, the dimensions of any system have been permanently scaling down to achieve the efficiency of Integrated Circuit (IC) since many decades. ICs have been waiting for a planar platform for a long time during their careful scaling. In the past few years, there have been two big requests. The primary demand is that the measurements of all devices have nearly reached a snag. Limiting the interconnect delay output of complete circuits or systems is the secondary and most significant demand. The most critical and real limitation is that there is none, but the interconnect delay is almost undistinguishable to that of the units. New interconnecting materials, as well as experimental architectures, must be designed to meet the demands of device efficiency. New integration methods called Three-Dimensional IC (3D IC) have been introduced to reduce interconnect delays. Noise coupling is a big issue in 3D IC. As a result, several researchers have applied and verified various materials through TSVs and substrates to minimize noise coupling issues. This paper presents an extensive survey on noise coupling reduction and future direction towards improvement of coupling issues in 3D IC.