InP MOSFETs Exhibiting Record 70 mV/dec Subthreshold Swing

Abstract

Low InP/dielectric interface trap density <tex>$D_{\\mathrm{it}}$</tex> will enable low subthreshold swings <tex>$(SS)$</tex> in mm-wave MOSFETs [1] using InGaAs/InP composite channels [2] for increased breakdown and in tunnel FETs (TFETs) [3] using InAs/InP heterojunctions [4] for increased tunneling probability. Reducing <tex>$D_{\\mathrm{it}}$</tex> at the etched InP mesa edges of DHBTs and avalanche photodiodes will reduce leakage currents and increase breakdown voltages. While it can be difficult [5] to extract <tex>$D_{\\mathrm{it}}$</tex> of III-V interfaces from MOSCAP characteristics, <tex>$D_{\\mathrm{it}}$</tex> can be readily determined from the <tex>$SS$</tex> of long gate length <tex>$L_{\\mathrm{g}}$</tex> MOSFETs. Here we report InP-channel MOSFETs with record low <tex>$SS$</tex> indicating record low <tex>$D_{\\mathrm{it}}$</tex> at the semiconductor-dielectric interface. The devices use an AlO<inf>x</inf>N<inf>y</inf>/ZrO<inf>2</inf>gate dielectric and a 14nm channel thickness <tex>$T_{\\mathrm{ch}}$</tex>. A sample of 13 MOSFETs at <tex>$2\\ \\mu \\mathrm{m}L_{\\mathrm{g}}$</tex> shows <tex>$SS=70\\mathrm{mV}/\\mathrm{dec}$</tex>. (mean) <tex>$\\pm 3\\mathrm{mV}/\\mathrm{dec}$</tex>. (standard deviation), corresponding to a minimum <tex>$D_{\\mathrm{it}}\\sim 3\\times 10^{12}\\mathrm{cm}^{-2}\\mathrm{eV}^{-1}$</tex>. The lowest <tex>$SS$</tex> observed at <tex>$2\\ \\mu \\mathrm{m}L_{\\mathrm{g}}$</tex> is 66mV/ dec. The results suggest that wide-bandgap InP layers can be incorporated into MOS device designs without large degradations in DC characteristics arising from interface defects.