Multi-Stack Wafer Bonding Demonstration utilizing Cu to Cu Hybrid Bonding and TSV enabling Diverse 3D Integration

Abstract

3D Multi-stacking technology using Cu-Cu hybrid wafer bonding has been developed to achieve superior power, speed performances and higher density with minimized form factor. To realize multi-stacked device by using Wafer on wafer (WoW) bonding, both Face-to-Face (F2F) and Back-to-Face (B2F) interconnection can be required for more efficient and simple I/O pad design as well as lower resistance thanks to shorter interconnections. In this paper, we successfully demonstrated wafer-level multi-stacking structure by applying robust Cu-to-Cu bonding combined with Through-Si-Via (TSV) process. Three key subjects of comprehensive understanding about bonding interface, TSV and edge engineering to avoid defects and yield drop were essential to fulfill this research. Chemical-Mechanical-Polishing (CMP) and surface treatment had a huge impact on the Cu/dielectric hybrid bonding surface. In particular, planarization at the backside of the wafer is the key technology for robust follow up wafer bonding. For TSV formation, etch advancement performed to control the enhanced target compared to existing scheme. One more key subject is the edge engineering including integration considered edge treatment and effect by the process has been conducted to improve wafer bonding quality and reproducibility. Through the optimization of multi-stack oriented processes and integration, we confirmed extremely high yield of electrical connection including wafer edge for multiple layers. Many valuable applications can be introduced for sensors, memories, logic devices and even combinations of them by utilizing this novel processes.