Novel Approach to Highly Robust Fine Pitch RDL Process

Abstract

Fan-out Wafer Level Packaging (FOWLP) is expected to become an indispensable platform for integrating heterogeneous chips into advanced semiconductor packaging for next generation edge computing, automotive and others. In order to integrate multiple memory and logic chiplets, the line/space (L/S) design rule of the Cu redistribution line (RDL) will be scaled below $2/2\\ \\mu\\mathrm{m}$ in order to accommodate the multiple chip configurations and high I/O count. While the current semi-additive process (SAP) used to manufacture the 1st generation of FOWLP technology has served the IT industry well, the absence of a physical diffusion barrier between the Cu and the polymer and the heavily undulated topology presents serious reliability and processing challenges. To overcome these limitations, this paper presents the first work published on fabrication of polymer damascene RDLs. RDLs were fabricated by dry-etching patterns into a polymer film, filled with electroplated Cu and planarized with CMP. The use of a Ti diffusion barrier prevents Cu migration into the polymer and the CMP process prevents any unwanted undulation that can adversely affect the line width uniformity. By developing a damascene integration scheme without the use of spin-on hardmasks and bottom anti-reflective coatings, we can keep the costs low without sacrificing the benefits of the damascene structure. Results show well defined RDLs with a robust Ti barrier limiting the diffusion of Cu into the polymer even after wafer level high temperature storage (HTS) testing. With the available technology, this integration scheme has the potential to extend the FOWLP design rule to well below $\\mathrm{1}\\ \\mu\\mathrm{m}$.