A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency

Abstract

This work presents a fast-transient and low-power, external-clock-less digital low-dropout regulator (DLDO) using a wide-range adaptive sampling frequency, $f_\\text{SP}$. To generate such an $f_\\text{SP}$, the proposed gear-shifting comparator (GSC) consists of two sub-comparators. First, in the transient state, a delay-line-based comparator (DLC) generating a high $f_\\text{SP}$ swiftly reduces the error in the output voltage, VERR. Second, in the steady state, a subsequent edge-racing comparator (ERC) generating a low $f_\\text{SP}$ slowly but accurately removes VERR. Using these two tightly-interlocking sub-comparators, the GSC can scale the $f_\\text{SP}$ dynamically in a wide range so that it can make the DLDO concurrently achieve a fast response in the transient state and a small quiescent current in the steady state. Due to the unique capability of the ERC, the DLDO also can have a high-accuracy regulation. The DLDO was fabricated in a 65-nm CMOS process, and it achieved a 46-ns settling time against the 12-mA change of the load current with a 100-ps edge time. The quiescent current was only 10 $\\mu \\mathrm{A}$. The transient FOM was 0.0084 mV, which was the best among the state-of-the-art DLDOs.