Nanowire & Nanosheet FETs for Ultra-Scaled, High-Density Logic and Memory Applications

Abstract

We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around (GAA) FET devices as promising candidates to obtain a better power-performance metric for logic applications for advanced sub-5nm technology nodes, in comparison to finFETs. In addition, vertical NW/ NS GAA FETs appear particularly attractive for enabling highly dense memory cells such as SRAMs (with improved read and write stability), and as the selector devices for ultra-scaled MRAMs with lower energy consumption values. These cells can be manufactured by a cost-effective, co-integration scheme with a finFET or NW/NS FET high-performance logic platform for increased on-chip memory content.