Accuracy Reconfigurable Adder for Low Power Of Sobel Edge Detection Algorithm

Abstract

A edge or contour on the edge of an image undergoes a significant shift in intensity levels. For these strong shifts in the images, edge detection is the technique adopted. The purpose of developing low power sobel edge detection in FPGA. The simple edge detection circuit was initially modified to cut the overall power consumption performed in software simulation with low power adders. The pixel values of the image are passed on to the Xilinx architecture. A limited selection of pixels is collected in order to acquire edges and non-edges, and absolute values relative to the predefined threshold value are calculated. If the gradient exceeds the threshold value it is known as a rim, otherwise it is discarded. The high computational complexity of multimedia applications is provided by rapid and energy processing power cores on mobile devices. The reliability of the arithmetic unit affects the machine’s overall output in these cores considerably. This paper therefore introduces a CLA-based carried look ahead and a new approach to approximate sum generation for the powerful precision reconfigurable adder (AR) architecture, namely ARCLA. The proposed architectures of AR-CLA can be reconfigured to provide high energy performance at the cost of a reasonable loss of consistency. In contrast to the current adder design figures the performance measures of the proposed adder designs as a standalone device show a significant improvement.