Design of SentiNet RTL Library for CNN based Hardware Accelerator

Abstract

Deep neural networks transfixed the contemporary world of humans, thereby enabling to obtain a better comprehension of diverse elements of the cognitive intelligence, which can be utilized to greatest advantage of creating innovative and unprecedented man made computer systems that can be self-taught to conclude on solutions for complex problems by itself. Contemporary times shows recent evolution in edge computing platforms that are used in implementing such complex cognitive networks. Such intricate systems always tend to be greedy towards memory usage and involves millions of computations. Recent trends provides testimony for usage of DNNs in various fields particularly focusing on Computer Vision applications. Convolutional Neural Networks or Conv Nets is being explored in the application of Face Detection along with Emotion Recognition and its implementation on real time embedded platforms such as FPGAs. Recognition of human faces and the emotions expressed by them needs a thorough understanding of the hallmarks of the emotions or sentiments irrespective of the emotion being perceived. In this paper we present a novel approach to design Register-Transfer - Level (RTL) library of SentiNet CNN model that can be mapped onto hardware resources of the FPGA boards. The RTL design incorporates an inimitable technique to handle floating point operations that helps to reduce the computational complexity. The design implementation was carried out for Zynq Ultra Scale+ZCU 106 evaluation board.