Research on Single-Event Vulnerability and Hardening for a Pipelined ADC

Abstract

Analog to digital converters (ADCs) are ubiquitously required in modern spaceborne electronic systems. However, as a continually shrink of the technology feature sizes, single-event effects (SEEs) such as single-event transients (SETs) and single-event upsets (SEUs) can significantly cause performance degradation of the data converters exposed to radiation environments. This paper analyzes SE vulnerability in pipelined ADC. Circuit-level radiation-hardened-by-design (RHBD) techniques for analog SET (ASET) and a system-level digital calibration method for radiation hardening are discussed. Based on the dual-path technique, a prototype radiation hardened 14-bit 1GSPS pipelined ADC based on 65nm CMOS process is designed. Simulation results show a SFDR value of 79.91dB for a 1.7VP-P 340.3MHz input sine wave at a sampling frequency of 1GHz with radiation immunity.