Evaluation of Double-Line-Frequency Power Flow in Solid-State Transformers

Abstract

Solid-state transformer (SST) directly steps medium voltage down to low voltage with minimized power conversion stages for higher overall efficiency. The Input Series Output Parallel (ISOP) structure is widely used consisting of Cascaded HBridge (CHB) and DC/DC converters. Such system architecture introduces a double-line-frequency power flow in the DC/DC stage. To deal with this fluctuating power, two main solutions are proposed by different researchers. In this paper, a detailed review is addressed on the comparison between the DC/DC stage with constant power flow, and with fluctuating power flow. For constant power flow method, the current stress in the DC/DC stage is lower, resulting in a higher efficiency with a sacrifice in the bus capacitor volume. For the fluctuating power flow method, the usage of the bus capacitor can be minimized with the efficiency reduction. The loss breakdown for the fluctuating power flow control is analyzed to find possibility to improve the efficiency. Two control methods are compared by an 15kW, 200kHz CLLC prototype with 98.9% peak efficiency.