High Yield and High Throughput Lithography Solution for Emerging High Density Fan-Out Panel Level Packaging

Abstract

The fan-out packaging (FOP) catches the general interest of microelectronics packaging, which has several advantages such as smaller formfactor, more efficient heat dissipation, better signal integrity, and higher reliability, matching with the requirements of advanced consumer electronics. It is, however, the reconstituted die shift and the carrier warpage have yet to overcome. These critical issues tighten the lithography overlay tolerance. Warpage issue can be controlled by suitable carrier selection. On the other hand, die shift can be well managed when following factors are taken into account: (1) carrier coefficient of thermal expansion (CTE) and thickness; (2) die/mold thickness and fan-out ratio; (3) shrinkage/expansion of involved materials. Fan-out panel level packaging (FOPLP) is considered a cost-effective solution owing to higher carrier usage ratio. However, the aforementioned challenges are aggravated by the fact that the panel is not centrosymmetric and has larger die placement area with respect to the traditional wafer form carrier. Mask-less laser direct imaging (LDI) lithography technology has been adopted as a potential solution to overcome large die shift by relaxing lithography overlay constraint. But the low throughput of LDI undermines the cost benefit of PLP. In this paper, we implement an off-line mapping system to collect and analyze the die shifts on a panel with size of 510mm ×515mm. The mapping data are subsequently introduced into a stepper to guide the PLP exposure process and achieve more than double the throughput. With proper die shift compensation, on top of the integrated mapping/exposure system, the throughput by using the full reticle exposure can be further enhanced to 20 times than that of die-by-die exposure. The integrated system can be utilized to predict lithography yield under the combination of different exposure field size and different overlay spec. By using the same system, we achieve a lithography yield of 99.9% within ±12um lithography overlay spec at the maximum field size.