Substrate Solder Resist Crack Root Cause Investigation Through Finite Element Analysis

Abstract

The solder resist crack root cause and methods to prevent it were studied. Solder resist crack with solder extrusion was observed in the sample package after solder ball mount. A finite element model was developed to simulate the solder resist stress. A high stress area at the bump pad edge was observed at the reflow peak temperature, which is the solder resist crack root cause. The factors affecting the solder resist stress were also studied via the finite element method. It was found that reflow temperature, underfill Young s modulus, substrate dielectrics CTE, and die-to-substrate ratio are the key factors to the solder resist stress. Strategies of using low Young s modulus underfill and small die-to-substrate ratio to reduce solder resist crack length were demonstrated through process DOE and design optimization in the test vehicle package.