Measurement Process Optimization in Using Lock-in Thermography for Fault Localization of CoWos Packages

Abstract

This paper mainly investigation on defect localization application of CoWos (Chip on Wafer on Substrate) packaging through lock-in thermography. When failure samples are rare, it is necessary to use non-destructive Thermal EMMI to detect hot spots, and determine the defect Z-depth of CoWos packaging by lock-in thermography and PFA (Physical failure analysis) methods. We found that at different lock-in frequencies, the amplitudes of the hot spots were basically 10mK, but during the second exposure of 3 minutes at different frequencies, the phase differed greatly, and not even every lock-in frequency could detect the effective hot spots. It is considerable to select the appropriate lock-in frequency to get the optimal hot spot for the fault. In this paper, the concept of standard deviation is introduced into the optimal choice of hot spots. The frequency with the minimum standard deviation of phase is selected as optimal condition for failure localization. The lock-in thermography can not only quickly determine the Z-depth of fault refer to good pin or phase of each structure of CoWos chip, but also select optimal hot spot XY coordinate through the standard deviation of phase. An optimal lock-in frequency of certain hot spot on die or substrate layer are identified through a series of experiments. It is noticeable that optimal hot spot through the minimum standard deviation of phase can impove the accuracy of fault location and the success rate of subsequent physical analysis.