A Module-Level Pipeline Implementation Based on Inter-Board Heterogeneous

Abstract

With the internet of things, autonomous driving, and smart security rapid development, data growth puts higher and more urgent requirements on processor computing performance. A single chip is hard to meet the real-time computing requirements in many scenarios, so it is necessary to expand multiple chips. This paper proposes a module-level pipeline FPGA cluster structure based on inter-board heterogeneous. The method divides a single enormous task into multiple modules and running each module on different FPGA as the pipeline structure between boards. In addition, considering the impact of communication delay between boards, it is proposed to use the delay between development boards as a separate stage of the pipeline. In this way, we can minimize a stage’s runtime of module level pipeline. In order to evaluate the calculate capacity of per hardware resource, the concept of resource conversion efficiency (RCE) is proposed. Experimental results of LeNet -5 neural network with the module-level pipeline structure design demonstrates that proposed method increased processing capacity and resource utilization efficiency. Compared with the method of sequential execution, the execution speed and RCE of the proposed method are increased by 46.1% and 84.7% respectively.