Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol

Abstract

Advanced Peripheral Bus (APB) is the piece of Advanced Microcontroller Bus Architecture (AMBA) family conventions. It is an easy interface and the arrangement is to improve the plan for the least possible power intake and diminished interface unpredictability. In contrast to AHB, it is a Non-Pipelined convention, used to associate low-data transfer capacity peripherals to the SoC. The 32-bit model is developed for communication between Master and Slave devices. The Testbench acts as a Master APB and Design acts as a Slave APB. The Master originates transports on the Peripheral Bus which supports Write, Read, and Idle exchanges. It likewise validates the most extreme number of slaves. Slave memory reaction displayed by arrangement. It upholds stand by states utilizing READY sign additionally bolsters error reaction utilizing ERROR signal. The fundamental point of the proposed work is to plan and examine the different functional aspect of the protocol. i.e. information read from a specific system area is the similar as the information written to the given system area and the protocol verifies the functionality by passing random value to same indexed address, random value for randomly indexed address and grouping write and read values together. The system embraced for the proposed work uses Verilog language and Verilog Testbench to extract synthesis, design usage synopsis. The design utilized Verilog programming which greatly enhances reusability of the Testbench components such as creating Tasks for various Test cases.