Paper Presentations (Abstract)

Abstract

This paper presents a class AB second generation voltage conveyor. This device is designed to obtain the current buffer as input stage and is followed by the voltage buffer in monolithic chip. A class AB technique to obtaining high signal swing, high dynamic range, high bandwidth and low power consumption has been used. The proposed circuit is simulated using SPICE simulations with a standard 0.18 um CMOS process level 8 and with +/-0.9 V supply. Paper ID : 1570556283 Paper Title : Fluoropolymer as Dielectric in Organic Field Effect Transistor (OFET) Authors : Nur Amiera Nor Halim; Mohd Nazim Mohtar; Muhammad M. Ramli; Roslina Mohd Sidek; Nur Zuraihan Abstract : Fluoropolymer is one type of dielectric material that have been used in Organic Thin Film Transistor (OTFT). It is the important part in OFET even though it is insulator material. Dielectric is supposedly acting as a capacitance. The concept of capacitance is to sort the electric field that can be used. There have unique characteristics that can be used for OTFT device. Low dielectric contact material is needed in ultra-large-scale integration (ULSI) to breakdown the parasitic capacitance that effect the value of current flow. By using drop cast as depositing method on interdigitated ITO, the length of channel is varied. Currentvoltage (I-V) measurement have been used to measure the resistance at the different channel length. The value of resistivity can give some impact to the OFET device. Fluoropolymer is one type of dielectric material that have been used in Organic Thin Film Transistor (OTFT). It is the important part in OFET even though it is insulator material. Dielectric is supposedly acting as a capacitance. The concept of capacitance is to sort the electric field that can be used. There have unique characteristics that can be used for OTFT device. Low dielectric contact material is needed in ultra-large-scale integration (ULSI) to breakdown the parasitic capacitance that effect the value of current flow. By using drop cast as depositing method on interdigitated ITO, the length of channel is varied. Currentvoltage (I-V) measurement have been used to measure the resistance at the different channel length. The value of resistivity can give some impact to the OFET device. Paper ID : 1570556452 Paper Title : A 800 μW, 2.4 GHz, Triple Cross Coupled Down-Conversion Mixer with 18 dB Conversion Gain in 65 nm CMOS Technology Authors : Chi Yi Lai; Harikrishnan Ramiah; Nandini Vitee; Jagadheswaran Rajendran Abstract : A 2.4 GHz folded mixer using 65 nm CMOS technology is presented in this paper. A triple cross-coupling technique is adopted to achieve low noise and high gain performance. Besides that, the transconductance stage are biased in subthreshold mode to further lower the power consumption of the architecture. This mixer exhibits a good conversion gain of about 18.28 dB with low power consumption of A 2.4 GHz folded mixer using 65 nm CMOS technology is presented in this paper. A triple cross-coupling technique is adopted to achieve low noise and high gain performance. Besides that, the transconductance stage are biased in subthreshold mode to further lower the power consumption of the architecture. This mixer exhibits a good conversion gain of about 18.28 dB with low power consumption of 0.82 mW from a 800 mV power supply. The noise figure is simulated to be 12.88 dB at 100 MHz IF frequency and the IIP3 is -6.562 dBm. This low power design is well adopted for Internet of Things (IoT) applications. Paper ID : 1570562819 Paper Title : A Method of Sinusoidal Phase Signal Correction Using Summing and Subtraction Topology for Improving Encoders Performance Authors : Lee Lini; Shabiul Islam Abstract : Encoders are angular and speed position sensors that are mainly used in a motor feedback system. There are several types of technology to design an encoder sensor ranging from optical system, magnetic system, capacitive system and inductive Encoders are angular and speed position sensors that are mainly used in a motor feedback system. There are several types of technology to design an encoder sensor ranging from optical system, magnetic system, capacitive system and inductive system. The choice of technology and the specifications of the encoder system will depend on the application usage. Some application requires an encoder to be small in size, low cost and only need to have the most basic of functions. In practice, the very basic of an encoder output needs to contain two signals which are 90 degrees apart. These signals generated from the sensors are crucial for the accuracy of the encoder but in reality these are not ideal. They will contain different amplitudes, phase shifts, dc offsets and noise due to the mechanical & electrical construction. This paper will present a method of improving phase shifts between the sinusoidal signals done in a simple analog blocks configuration that does not need digital processing which is suitable to be used in a small size and low cost encoders. The method will be modelled and simulated first in MATLAB and then implement into the analog blocks using TSMC 0.25um process. Results of the simulation from the analog implementation will be presented to show the improvement in the phase errors. Date : Wednesday, 18 September 2019 Session : Digital Circuits & Systems Time : 11.30 12.50 Room : Ruby Session Chair : Fakhrul Zaman Rokhani Paper ID : 1570546359 Paper Title : Design and Practical Implementation of Two-Port Network Analyzer for Microwave Measurement from 200 MHz to 2.7 GHz Authors : Chamath Kalanaka Vithanawasam; Yi Lung Then; Su Hieng Tiong Abstract : Network Analyzers are commonly utilized in measuring various radio frequency (RF) and microwave measurements. In many cases Vector Network Analyzers (VNA) are available and are better suited given their ability to measure the magnitude and phase results for a device under test (DUT). These devices are, however, bulky and expensive, therefore limiting the amount of people who can have access to one of them. Due to these drawbacks, a low-cost two-port network analyzer was designed for optimum operation at frequencies from 200 MHz to 2.7 GHz. Assembly of this device brought together the combined efforts of a SynthHD signal generator, 2 AD8302 RF/IF gain/phase detectors, couplers, and a Raspberry Pi 3 Model B, which was used to program a graphical user interface (GUI), capable of plotting Sparameter readings. A commonly used error calibration method was also used to eliminate common errors. Network Analyzers are commonly utilized in measuring various radio frequency (RF) and microwave measurements. In many cases Vector Network Analyzers (VNA) are available and are better suited given their ability to measure the magnitude and phase results for a device under test (DUT). These devices are, however, bulky and expensive, therefore limiting the amount of people who can have access to one of them. Due to these drawbacks, a low-cost two-port network analyzer was designed for optimum operation at frequencies from 200 MHz to 2.7 GHz. Assembly of this device brought together the combined efforts of a SynthHD signal generator, 2 AD8302 RF/IF gain/phase detectors, couplers, and a Raspberry Pi 3 Model B, which was used to program a graphical user interface (GUI), capable of plotting Sparameter readings. A commonly used error calibration method was also used to eliminate common errors. Paper ID : 1570550484 Paper Title : A New Twiddle Factor Merging Method for Low Complexity and High Speed FFT Architecture Authors : Xueyu Han; Jiajia Chen; Susanto Rahardja Abstract : FFT is one of the most widely-used algorithms in signal processing and communications applications. Although its realization in hardware-efficient FFT designs has been studied, there is still room to further reduce the complexity of FFT architectures by exploring more efficient expressions of twiddle factors in the FFT coefficients. In this paper, a new 16-point FFT architecture is designed. A twiddle factor merging method is proposed to reduce the number of multiplications, additions and subtractions used in the design. To further improve the design, we apply a common subexpression sharing scheme to optimize the hardware resource sharing among the twiddle factors. Compared with previously published method, the proposed 16-point FFT architecture gains 25.4% and 14% improvement on hardware cost and delay respectively. FFT is one of the most widely-used algorithms in signal processing and communications applications. Although its realization in hardware-efficient FFT designs has been studied, there is still room to further reduce the complexity of FFT architectures by exploring more efficient expressions of twiddle factors in the FFT coefficients. In this paper, a new 16-point FFT architecture is designed. A twiddle factor merging method is proposed to reduce the number of multiplications, additions and subtractions used in the design. To further improve the design, we apply a common subexpression sharing scheme to optimize the hardware resource sharing among the twiddle factors. Compared with previously published method, the proposed 16-point FFT architecture gains 25.4% and 14% improvement on hardware cost and delay respectively. Paper ID : 1570563823 Paper Title : 3-Bit Digital Electro-Optic Odd Parity Generator Based on Photonic Micro-Ring Resonator Authors : Foo Kui Law; Mohammad Rakib Uddin; Angie Teo; Abdul Hadi Abstract : This work presents the design, simulation and analysis of the 3-bit electro-optic parity generator circuit with silicon micro-ring resonator as its base component. The micro-ring resonator incorporates the PIN diode structure to enable the electrooptic free carrier diffusion effect. Two silicon micro-ring resonators are configured, where one of them operates as an XOR gate while the other operates as an XNOR This work presents the design, simulation and analysis of the 3-bit electro-optic parity