Poet: A Power Efficient Hybrid Optical NoC Topology for Heterogeneous CPU-GPU Systems

Abstract

Heterogeneous multi-core is an effective method to realize high performance computing. To integrate CPU and GPU via Network on Chip (NoC), taking advantages of concurrent communication and scalability, the expensive conventional off-chip data transmission can be avoided. The electric NoC (ENoC) has the advantage of low latency and low power consumption in the local short-distance communication, however, the hop to hop communication mechanism in traditional electric NoC causes higher power consumption and latency. Optical NoC (ONoC) provides an alternative to traditional interconnection scheme to reduce communication latency but the static power consumption of ONoC increases nonlinearly with the increase in number of interconnected nodes. So it is vital to design a hybrid electrical-optical NoC (HNoC) to reduce latency and power consumption taking advantages of both electrical and optical interconnections. We propose Poet, a HNoC architecture for heterogeneous system, which is used to alleviate the bandwidth bottleneck caused by data-intensive communication in intelligent applications and reduce static power consumption in order to adapt to the different communication demands. Poet uses modified Reservation-based Single Write Multiple Reader (R-SWMR) optical bus for long distance communication and low latency data communication. Use electric layer for short distance communication reduced number of microrings. Experimental results depict that power consumption has been reduced by 12.5% in comparison to heterogeneous architecture called Sharp and the latency has been reduced 76.61% compared to the E-Mesh under the same scale architecture of uniform random traffic.