PCB Strip Scale Numerical Study on Vacuum Molded Underfill Void Entrapment in FC-POP Devices

Abstract

Molded underfill process provides many benefits over capillary underfill process, but increased void defects in molded underfill process could cause pop-corning effect and solder extrusion during the reflow process. This paper presents a highly efficient and accurate hybrid model that can be applied to diagnose the void risk in vacuum molded underfill processes of real flip-chip, package-on-package devices with complex ball arrays and large PCB strips. The model utilizes multi-zone porous media model, Hele-Shaw model and compressible two-phase computational fluid dynamics model. The model has been well validated in terms of the entrapped void size and its behavior with flow visualization experiments. Not only the model provides better understanding of the physics of void entrapment but also is proven to be an effective tool for assessing the potential void risk through its application to 10nm flip-chip, package-on-package device mass production line.