Hardware Architecture for Acquisition in IRNSS Receiver using Serial Search Method

Abstract

Indian Regional Navigation Satellite System (IRNSS) is an independent, indigenously developed satellite navigation system by India. The ASIC design of the digital baseband receiver is the major requirement of any IRNSS handheld device for navigation. This work focuses on design and implementation of IRNSS signal acquisition in time domain. The major challenge in the time domain approach is the increase in acquisition time. By taking advantage of the straight forward implementation with less resource the serial search acquisition is designed by parallelizing frequency search for all carrier frequency bins considering maximum Doppler shift in the range of +/-10KHz with 500Hz resolution and code phase using serial search for half chip resolution. The numerically controlled oscillators are designed using quarter sine wave look-up table supporting a minimum resolution of 0.015Hz. The decision for the presence of the signal is done on the run without storing the intermediate results thereby reducing the memory requirement. The code is implemented in RTL (Register Transfer Level) using VHDL without using any third party IP core. The prototype is validated by implementing in Xilinx XC7Z045FFG900-2 FPGA. The acquisition time obtained is 1.023s for one satellite and the resources utilized is less (as given in Table-1).