A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC

Abstract

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle quantization to improve the conversion speed. In addition, by obtaining reference delays with duplicated circuits and using non-binary capacitor arrays, the ADC can tolerate process, voltage and temperature (PVT) variations and decision errors. To validate these concepts, a 10-bit 2 MS/s SAR ADC is designed using 130nm CMOS process with 0.5 V power supply voltage. Simulation results shows the ADC achieve signal-to-noise distortion ratio (SNDR) of 59.63 dB, corresponding to an effective number of bits (ENOB) of 9.61 bits and consumes 3.2 µW, resulting in a figure of merit (FOM) of 2.06 fJ/c-s.