Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs

Abstract

A double-comparison capacitive digital-to-analog converter (CDAC) settling error correction scheme for binary scaled successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed in this paper. In the proposed scheme, two comparators make their decisions sequentially within each conversion cycle to guarantee the correctness of the decisions, while allowing the CDAC settling overlap with comparator and logic operations. Compared to conventional settling error correction techniques, the proposed scheme potentially relaxes the settling requirement without additional capacitors and extra conversion cycles. The effectiveness of the scheme is verified by a 500MS/s 8-bit SAR ADC in 55 nm CMOS technology. The settling time for the maximum possible voltage shift is reduced by 72%. The ADC core occupies 0.017mm2 and consumes 2.69mW from 1.2V supply. The proposed ADC achieves an averaged 45.8dB SNDR in the first Nyquist zone which indicates an improvement of 3dB compared to conventional ADC.