Improving SNDR and SFDR in Capacitive DACs using Match Enhancement

Abstract

The power consumption of moderate resolution SAR ADCs, commonly used in IoT applications such as implantable medical devices and wireless sensor nodes, is often limited by capacitor matching requirements. This paper presents an experimental realization of match enhancement, a technique that reduces the variation of binary-weighted capacitors by combining unit capacitors with errors of comparable magnitude and opposite polarity to reduce their net error contribution. Using an on-chip ΔC-to-Δf capacitance measurement circuit to quantify each capacitor s relative error and an intelligent capacitor assignment algorithm, match enhancement significantly relaxes the matching requirement. A prototype SAR ADC was designed, fabricated in 180 nm CMOS, and tested to demonstrate the effectiveness of match enhancement. A unit capacitance of 705 aF and an area of 1.53 μm2 is obtained from a custom-designed metal-metal (M4-M5) capacitor. The SAR ADC has an active area of 0.48 mm2 and dissipates 2.34 μW at a 100 kS/s sampling rate with a 1.1 V supply. Match enhancement provides an average increase of 5 dB in SNDR and 12.3 dB in SFDR for the 75 devices tested. This work achieves a 29 fJ/C-s Walden FOM.